An all-digital IF GPS synchronizer for portable applications
Won Namgoong, S. Reader, T. Meng · 2003
GPS receivers typically employ an ASIC to compute correlation values and a general purpose DSP processor to perform the remaining digital processing operations. While this approach offers design flexibility, it is not well suited for portable applications because of relatively large power consumption and poor integration. Instead, an integrated GPS receiver that performs all of the digital processing is desirable. Toward that end, a power efficient highly-integrated GPS synchronizer is presented. The input to the GPS receiver chip is a 2 b data stream of sampled IF signal. The minimum operational frequency is 24 MHz at 1.5 V supply. The chip processes five channels and provides pseudorange estimates and navigation data. It is designed in 0.5 /spl mu/m CMOS technology. One design objective is to demonstrate that all of the required GPS synchronization operations can be integrated at a minimum power level.