Fault tolerant mesh based Network-on-Chip architecture
Navonil Chatterjee, Santanu Chattopadhyay · 2015
In this paper we present a fault tolerant Mesh based Network-on-Chip design that helps to tolerate router faults along with core recovery mechanism. Spare links are used to provide a connection to horizontal and vertical routers pivoting the failed one. To compliment the modified topology a routing algorithm has been developed that uses minimal and non minimal paths to communicate between source and destination IP blocks. The system has been compared in terms of reliability and mean time to failure (MTTF) and with existing works. The performance evaluation in terms of throughput and latency has also been reported.