An expandable chip design for gray-scale morphological operations
Ming‐Hwa Sheu, Jie Wang, J.-Y. Lee, L.-Y. Liu · 1993 IEEE International Symposium on Circuits and Systems · 2002
A new pipeline architecture to perform 3 /spl times/ 3 gray-scale morphological operations in real time is presented. This architecture has both lower hardware cost and faster operation time than other presented architectures. Under 1.2-mm CMOS technique, this architecture is implemented as one chip with 0.5 /spl times/ 0.6 cm/sup 2/ area size. The chip can be used as a basic building block to construct a chip size for any larger size morphological operations.>