Transaction level modeling of SoC with SystemC 2.0
Sudeep Pasricha · 2004
System architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. These activities are crucial and must be addressed at an early stage to prevent costly redesign effort later in the design cycle which can adversely affect time-to-market. SystemC 2.0 facilitates the development of Transaction Level Models (TLMs) which are models of the hardware system components at a high level of abstraction. System architects can quicklyion. System architects can quickly develop these models and be ready with an executable specification of the hardware blocks as soon as the initial functional specifications of the system are decided. The high speed of simulation of these TLMs allows early development and verification of hardware dependent application software. Timing details can be incorporated into these models to allow performance estimation and architecture exploration. The modular nature of SystemC also promotes reuse of developed components from one system to another. This paper elaborates on the concepts mentioned above and introduces an example SoC TLM platform.