Novel VLSI Architecture of Motion Estimation for H.264 Standard
Xiang Li, Rajiv Chopra, Kenneth W. Hsu · 2005
A novel architecture to achieve real-time motion estimation compensation encoding for H.264 ITU video compression standard is presented. A full-search block matching algorithm has been adapted to a pipelined data flow to enable parallel processing of variable block sized block matching and fractional pixel motion vector generation. The SOC is designed with TSMC 0.18/spl mu/m technology using VHDL and optimized to achieve a 125 MHz clock speed to make real-time processing possible.