A 100 MHz FPGA based floating point adder
D. Narasimhan, Darlan Alexandria Fernandes, V. Raj, J. Dorenbosch, Mark D. Bowden, V.S. Kapoor · 2002
The authors present the design of a floating-point adder implemented on a FPGA (field programmable gate array) that operates at 100 MHz. High-speed submicron technology FPGAs with a large number of logic blocks, which increased routing facility, were combined with a well-partitioned design. This adder adds two 13-b numbers and is implemented as an 8-stage pipeline.