A technique to design delay-insensitive VLSI circuits
Jo Ebergen · Centrum Wiskunde & Informatica (CWI), the national research institute for mathematics and computer science in the Netherlands · 1986
A technique for a hierachical design of delay-insensitive circuits is presented.The techniques are developed by means of the trace-theory formalism.The design consists of the formulation of a specification and its decomposition into basic elements.Parallelism is allowed in a specification.The notion of delay-insensitive circuit is formalized.Three examples are given to illustrate the technique.