A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators
Hiroyuki Mizuno, Nozomu Matsuzaki, K. Osada, T. Shinbo, N. Ooki, H. Ishida, K. Ishibashi, T. Kure · 2002
This cache operates at 10 mW, and 100 MHz at 1 V supply using separated bit-line memory hierarchy architecture (SBMHA) that reduces latency and power, and domino tag comparators (DTCs) that reduce dissipation of tag comparisons. On-chip caches in low-power microprocessors need high bit-ratio to reduce power. Higher bit-ratio is achieved using a larger cache. But this has the drawback of longer latency. The SBMHA hides the long latency.