SuperV back-end design flow based on astro
Wang Dong-Hui, Yu Qian, Hong Ying, Chaohuan Hou · 2006
In deep sub-micron VLSI design, designers must face many challenges including timing, area, power, IR drop, crosstalk, etc. A back-end design flow is put forward based on Astro. The flow has been used in SuperV DSP microprocessor back-end design for timing optimization, area and IR drop reduction, crosstalk prevention, etc. The final chip includes more than 1 million gates. The area is 5 mm /spl times/ 5 mm. The clock frequency is up to 266 MHz, and power dissipation no more than 1 watt.