A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology
Azeddien M. Sllame · IEEE International Workshop on System-on-Chip for Real-Time Applications · 2004
This paper presents a proposal for reusable hardware core (component) model. The model is designed based on the knowledge gained by the exploiting the design space exploration methodology presented in (Sllame, 2003). The model structure contains component characterization, computation core specified in VHDL language, a test bench to smooth the component integration process within the application and interfacing.