A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond
K.-T. Park, Jinyoung Choi, Jongsun Sel, V. G. Kim, Chan Young Kang, Youngsoo Shin, Ukjin Roh, Jung Ock Park, Jang‐Sik Lee, Jae Eun Sim, Sejun Jeon, C. Lee, Kyu Hong Kim · 2006
A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements