Access optimizer to overcome the "future walls of embedded DRAMs" in the era of systems on silicon
Takao Watanabe, Kazushige Ayukawa, Seiji Miura, Makoto Toda, Tetsuya Iwamura, Kouichi Hoshi, Jun Sato, Kazumasa Yanagisawa · 2003
This paper proposes an "access optimizer", a logic attachment for embedded DRAMs, which solves issues in the coming era of systems on silicon. The current embedded DRAM architecture relying on its large number of I/O lines will inherently face new walls. The long first access time causes the bottleneck between an on-chip CPU and an embedded-DRAM macro. The access conflict with the increase of embedded-DRAM masters will significantly degrade the chip performance.