Architecture template with dynamic buffering for runtime reconfiguration of adaptive embedded communication systems
Dirk Eilers, Helmut Steckenbiller, Rudi Knorr · 2003
This contribution introduces a distributed dynamic buffering scheme for runtime reconfiguration in adaptive processing architectures, e.g., for streaming media applications. With dynamic reconfiguration, area-cost of field-programmable logic (FPL) can be reduced by reuse and potential for adaptive signal processing techniques can be enabled. The challenge with runtime reconfiguration is the reconfiguration latency. Given the limitations with traditional approaches, we propose a distributed dynamic buffering scheme to hide latency. The simulation results show that our approach enables potential for runtime reconfiguration for adaptive signal processing under real-time constraints. Finally, we derive an architecture template with implementation details of the dynamic buffer scheme.