The clock distribution of the POWER4 microprocessor
Phillip J. Restle, C.A. Carter, J.P. Eckhardt, B. Krauter, Bradley D. McCredie, Keith A. Jenkins, Alan J. Weger, Anthony V. Mulé · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2005
The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.