Testability synthesis for jumping carry adder
M. Wagh, C.-I.H. Chen · 2003
Synthesis for testability process ensures that the design is testable, which exploits the fundamental relationships between don't care and redundancy in combinational and sequential circuits. In this paper a testability synthesis with redundancy removal for designing high speed jumping carry adders is presented. The 1.2 /spl mu/m CMOS realization of the 32-bit testable adder performs the addition operation in 4.09 ns. Removal of redundant logic yields a 100% testable design with significant improvement in performance. A 15% improvement in speed and a 25% reduction in overall area has been observed when compared with the untestable design.