Submicron BiCMOS technologies for supercomputer and high speed system implementation
B. Bastani, M. Biswal, Ali A. Iranmanesh, C. Lage, L. Bouknight, Vida Ilderem, Alan G. Solheim, Wolfgang Bürger, Rajeeva Lahri, J. Small · 2002
Submicron process technologies that allow a full implementation of CPU, first-level cache, second-level cache, and the main memory in the BiCMOS approach are described. CPU standard cells up to 100 K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 cache memories, and 1-Meg ECL I/O SRAMs with less than 7-ns access time have been achieved.>