500 MHz testing on a 100 MHz tester
Didier Wimmers, Kris Sakaitani, Burnell G. West · 2002
This paper describes an innovative way to test certain classes of complex digital devices at speeds of 500 MHz or more in a 100 MHz tester whose architecture incorporates the ability to generate a large number of edges per tester period. The means for generating the test patterns, and the means for executing them, are both described.