Adaptive design method for efficient direct digital synthesis
J.W. Bruce, J.E. Creekmore, Ben J. Blalock · 2003
In this paper, an area and power efficient ROM-less DDFS circuit with sinusoidal output is proposed. Sinusoidal spaced reference voltages are generated using an integrated resistor with a complex geometry. A DDFS accumulator output controls the nonlinear sinusoidal DAC directly and without the power-hungry ROM. The proposed design is independent of sheet resistance, and voltage reference power dissipation can be tailored to the application. Photolithography limitations can introduce geometry errors, thus, reference voltage errors. An adaptive design algorithm is proposed that reduces reference errors by more than an order of magnitude compared to the prior method. Finally, measurement results from a prototype 0.5 /spl mu/m CMOS implementation are presented.