Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation
Kah-Howe Tan, Wen Fung-Leong, S. Kadam, Michael A. Soderstrand, Louis G. Johnson · 2002
Savings ranging from 36% to 53% in FPGA resources are achieved through a filter design program that simultaneously applies optimum scaling, careful selection of filter order and use of fixed-coefficient multipliers designed with CSD and/or DM techniques. The output of the program is a VHDL description of the optimized hardware that is suitable as input to the Synplify Pro computer program that generates highly optimized FPGA circuits for Xilinx and other FPGA's.