Fault injection for verifying testability at the VHDL level
S.R. Seward, Parag K. Lala · 2004
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system. 1.