An SoC with two multimedia DSPs and a RISC core for video compression applications
H.-J. Stolberg, Sören Moch, Lars Friebe, A. Dehnhardt, Mark B. Kulaczewski, Mladen Bereković, P. Pirsch · 2004
An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip is implemented in a 0.18/spl mu/m 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.