CMOS artificial neuron on the base of β-driven threshold element
Victor I. Varshavsky · 2002
The task of hardware (CMOS) implementation of artificial neuron is discussed. The main part of the device is a /spl beta/-comparator which is a voltage divider formed by p- and n-transistors. This approach is based on the possibility of ratio form representation of an arbitrary threshold function. The weight of the input is determined by the limitation of the current through the n-transistor that is equivalent to changing its actual /spl beta/. The synapse itself consists of two (input and controlling) n-transistors. The full circuit of the learnable synapse with capacitor memory contains 5 transistors and a resistor that determines the time constant of learning. The results of SPICE-simulation are given.