Low power and hardware cost STUMPS BIST
N. Ravi Kiran, Gangadharappa Harish, A. Karthik, Siva Sankar Yellampalli · 2015
Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and ensures the testability of combinational logic present between flops used for constructing LFSR. The proposed BIST is tested with standard ISCAS'89 benchmark circuits and the experimental results shows that the proposed BIST averagely reduces the area overhead by 25.6 % and power overhead by 22.3 %.