Storage hierarchy to support a 600 MHz G5 S/390 microprocessor
P. R. Turgeon, Pak-kin Mak, D. Plass, M. Blake, M. Fee, Markus Fischer, Christopher Ford, G. Holmes, K. Jackson, C. C. Jones, K. W. Kark, Frank Malgioglio, P. J. Meaney, E. Pell, W. Scarpero, A.R. Seigler, Wei Shen, G. E. Strait, G. Vanhuben, G. C. Wellwood · 2003
Although a microprocessor's maximum frequency and internal design are important, the storage hierarchy is the primary reason for the large system performance improvement of the S/390 G5 compared to the G4. The improvement is achieved with an L2 cache, system controller and memory interface clocked at 1/4 the microprocessor frequency.