A basic-cell buffer 440K-transistor CMOS masterslice
Tomoya Arakawa, M. Ueda, Y. Saito, T. Fujimura, Sotoju Asai, Masayuki Terai, Y. Akasaka, Y. Kuramitsu · 1986
A masterslice containing 437,976 transistors on a 12.7×11.96mm2chip and employing a gate-isolation concept with no fixed routing tracks and no dedicated buffers, will be reported. The masterslice has been fabricated in 1.3μm CMOS technology. A 13MHz facsimile processor has been implemented using this array.