Analysis of effects of using exponent adders in IEEE-754 multiplier by VHDL
Ragini Parte, Jitendra Kumar Jain · 2015
Floating point arithmetic has a vast applications in DSP, digital computers, robots due to its ability to represent very small numbers and big numbers as well as signed numbers and unsigned numbers. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Here we analyze the effects of using three different types of adders while calculating the single precision and double precision floating point multiplication. We also present the multiplication of significand bits by decomposition of operands method for IEEE 754 standard.