Design of a Shared Scalable Buffer ATM Switch Embedded Low-Power SPRAMS
Gab Joong Jeong, Moon Key Lee · Journal of Electrical Engineering and Information Science · 1998
This paper describes an asynchronous transfer mode (ATM) switch architecture called shared scalable buffer ATM switch and its VLSI implementation. The shared scalable buffer ATM switch on one chip has embedded 4ns scalable pipelined RAM system (SPRAMS). It solves the restriction of memory cycle time in a shared buffer ATM switch. It supports flexible switching performance by the scalability of SPRAMS. It provides port size scalability with simple address control scheme. The performance evaluation was carried out on various switch configurations in uniform random traffic and uniform bursty traffic. The prototype chip has been designed for a 4 × 4 ATM switch that has a shared buffer of 128-cell. It is integrated in 0.6㎛ twin well, double-metal, and single-poly CMOS technology. The operating frequency is 80MHz, The core size is 10.6 × 10.6mm², and it supports 640 Mbps per port.