An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS
A.G.M. Strollo, Nicola Petra, D. De Caro, Ettore Napoli · 2004
In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 /spl mu/m CMOS technology, compares favourably with recently proposed RS decoders.