VLSI Architectures for JPEG2000
Tinku Acharya, Ping‐Sing Tsai · 2004
In this chapter, we have presented a VLSI architecture for the JPEG2000 encoder. We also presented the underlying details of the EBCOT architecture including its key building blocks and control mechanism. We presented the MQ-coder architecture for binary arithmetic coding. We also briefly presented the JPEG2000 decoder architecture which is architecturally similar with the encoder architecture with the data flow just in reverse direction with minor changes in the control mechanism and registers. There are not many architectures for the JPEG2000 algorithm available in the literature. Since entropy coding of the JPEG2000 is the most computationally intensive, few researchers focused on optimizing the EBCOT architecture in order to reduce clock cycle and memory requirements. We have reviewed these architectures in this chapter as well. Detail review of the VLSI architectures for lifting-based Discrete Wavelet Transform suitable for JPEG2000 has been presented in Chapter 5.