SOC design methodologies : IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France
Ifip Tc, Michel Robert · Kluwer Academic Publishers eBooks · 2002
Preface. Conference Committees. Architecture for Signal & Image Processing. Two ASIC for Low and Middle Levels of Real Time Image Processing P. Lamaty, et al. 64 x 64 Pixels General Purpose Digital Vision Chip T. Komuro, M. Ishikawa. A Vision System on Chip for Industrial Control E. Senn, E. Martin.Fast Recursive Implementation of the Gaussian Filter D. Demigny, L. Kessal, J. Pons. Dynamically Re-configurable Architectures. A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals R. David, et al. Dynamically Reconfigurable Architectures for Digital Signal Processing Application G. Sassatelli, et al. Reconfigurable Architecture Using High Speed FPGA L. Kessal, et al. CAD Tools. Design Technology for Systems-on-Chip R. Camposano, D. MacMillen. Distributed Collaborative Design over Cave2 Framework L.S. Indrusiak, et al. High Performance Java Hardware Engine and Software Kernel for Embedded Systems M.H. Miki, et al. An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures J.C. Otero, F.R. Wagner. Interconnect Capacitance Modelling in a VDSM CMOS Technology D. Bernard, et al. IP Design & Reuse. Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design C. Araujo, E. Barros. An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms G. Ascia, et al. Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 mum Bulk and Silicon-On-Insulator CMOS Technologies A. Neve, D. Flandre. High Level Design Methodologies. A Standardized Co-simulation Backbone B.A. De Mello, F.R. Wagner. Automatic Code-Transformation and Architecture Refinementfor Application-Specific Multiprocessor SoCs with Shared Memory S. Meftali, et al. Power Issues. Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model C.H. Gebotys, R. Muresan. Power Consumption Model for the DSP OAK Processor P. Guitton-Ouhamou, C. Belleudy. Design for Specific Constraints. Integration of Robustness in the Design of a Cell J.M. Dutertre, et al. Impact of Technology Spreading on MEMS design Robustness V. Beroulle, et al. Architectures. A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation N. Roma, L. Sousa. Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder S.M. Pisuk, P.H. Wu. Low Power, Low Voltage. Low-Voltage Embedded-RAM Technology: Present and Future K. Itoh, H. Mizuno. Low-Voltage 0,25 mm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors B. Curran, et al. Gate Sizing for Low Power Design P. Maurine, et al. Timing Issues. Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems J-B. Rigaud, et al. Feasible Delay Bound Definition N. Azemard, et al. Advance in Mixed Signal. CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors J.H. Choi, S. Bampi. A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor C. Lallement, et al. Verification & Validation. Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths P. Johannsen, R. Drechsler. Functional Test Generation using Constraint Logic Programming Z. Zeng, et al. Test.