A 256K dual port memory
S. Ishimoto, A. Nagami, Hirohito Watanabe, J. Kiyono, N. Hirakawa, Y. Okuyami, F. Hosokawa, K. Tokushige · 1985
This paper will describe a 64K×4 DRAM and a 256×4 serial readout memory with an access time of 35ns developed to provide graphic data pickup from any location. The ×4 DRAM port affords independent write capability for each bit in the word.