A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology
Seungjae Lee, Young-Taek Lee, Wook-Kee Han, Donghwan Kim, Moo‐Sung Kim, Seunghyun Moon, Hyun Chul Cho, Jungwoo Lee, Dae-Seok Byeon, Young-Ho Lim, Hyung-Suk Kim, Sung‐Hoi Hur, Kang-Deog Suh · 2004
A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.