Towards an Abstraction Hierarchy for CAETI Architectures, and Possible Applications
David C. Luckham, James Vera, Frank C. Belz · 1997
ion Hierarchy for CAETI Architectures, and Possible Applications. David Luckham, James Vera, Frank Belz (TRW) Program Analysis and Verification Group Computer Systems Lab Stanford University and TRW June 5, 1997 Abstract This document proposes a four level abstraction hierarchy for CAETI systems architectures for review and discussion by the CAETI community. Some possible applications are described briefly. 1 Introduction It has become customary to describe families of systems at distinct levels of abstraction. For example, levels of computer hardware generally include (i) instruction set level, (ii) register level, and (iii) gate level; there may be other levels too. Another example is the standard seven level hierarchy of the ISO OSI inter-connection reference model for network-based systems [?]. This is illustrated in Figure ??. At each abstraction level, specific concepts and components are introduced for defining architectures at that level. At each level, a particular syst...