An fpga implementation of real-time retinex video image enhancement
Hiroshi Tsutsui, Hideyuki Nakamura, Ryoji Hashimoto, Hiroyuki Okuhata, Takao Onoye · World Automation Congress · 2010
In this paper, we present an FPGA implementation of real-time Retinex video image enhancement. Our implementation is based on the previously proposed architecture, which can handle the variational approach of the Retinex theory. In order to efficiently reduce the enormous computational cost required for image enhancement, processing layers and repeat counts of iterations are determined in accordance with software evaluation result. As for processing architecture, our pipelining architecture can handle high resolution pictures in real-time. Our FPGA implementation supports WUXGA (1,920×1,200) 60 fps as well as 1080p60.