A high performance IIR digital filter chip
Roger Woods, John V McCanny, S.C. Knowles, O.C. McNally · 2002
The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-bit parallel, two's complement input data with a 12-bit parallel two's complement coefficient to produce a 14-bit two's complement output. The chip is implemented in 1.5- mu m, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.>