Measurement of glitches based on variable gate delay model using VHDL simulator
Tadashi Seko, Akihiro Nakamura, Tohru Kikuno · 2002
In this paper we propose a new method to measure the number of glitches of a circuit based on variable gate delay model, and then develop the VHDL simulator augmented with an evaluator which implements the proposed method. The application to adders and multipliers shows the usefulness of the proposed method.