The design of a GaAs micro-supercomputer
Trevor Mudge, Richard B. Brown, William P. Birmingham, J.A. Dykstra, Ayman Kayssi, R.J. Lomax, Kunle Olukotun, Karem A. Sakallah · 2002
The paper is an overview of the architecture, technology and CAD tools used in the design of an experimental 250 MHz 'micro-supercomputer' which is being designed for a sustained performance of 170 MIPS. The system will include a gallium arsenide processor which executes the MIPS instruction set and a two-level cache memory system, packaged on a multi-chip module. The risk in undertaking this project is minimized by using existing but advanced GaAs technology (GaAs MESFET enhancement/depletion direct-coupled FET logic (E/D DCFL)), by building needed CAD tools on top of commercial tools, and by using a standard instruction-set architecture.>