Bipolar merged arithmetic for wavelet architectures
G. Choe, Earl E. Swartzlander · 2003
Bipolar merged arithmetic is introduced to compute wavelet transforms efficiently. The proposed idea is suitable for implementing FIR filters with canonical signed digits. It introduces bipolar reduction segregating bit-product terms into two separate matrices; one with positive and the other with negative values. The bipolar merged arithmetic utilizes separate data paths to handle the negative data and the positive data. For fixed filter coefficients, bit-product elimination increases the speed of operation and reduces the complexity. The bipolar reduction requires a backend adder with two parallel adders and one subtracter which can be combined into an optimized fast logic or implemented as a less complex logic for a 2-stage pipeline.