A second level multiprocessing cache for the i486DX and i860XP processors
A. Golbert, B. Farrell, P. MacWilliams, N. Sakran, I. Silas · 2003
The objective of the present work is to be a primer on the 82495/82490 cache. The authors introduce the basic architecture elements of the solution, and describe in detail the motivations for the chosen architecture. The 495/490 cache uses an innovative architecture with frequency scalability in mind. The cache supports the i486 DX and i860 XP processors, working at 50 MHz. A detailed description of the architecture of the 82495 and 82490 is provided. Special emphasis is given to the innovative architecture elements such as the handling of 2-way associative through the MRU (most-recently-used) scheme, and the handling of the multiprocessing MESI protocol in a hierarchy of L1 and L2 caches. Lastly, the authors provide performance results from simulations and system benchmarkings of the 82495/82490 cache. >