Tutorial 3 High-level Design Validation And Test
S. Dey, Jay Abraham, Y. Zorian · International Conference on Computer Aided Design · 1998
Summary form only given. This tutorial is intended for desi<%nersC, AD tool developers, and researchers interested in addressing verification and test of VLSI systems at higher levels of abstraction, including verification and test of processors, general ASICs, and hardware-software system chips.