Multimedia SoC: a systolic core for embedded DCT evaluation
F. Cariccia, P. Cariccia, Maurizio Martina, Andrea R. Molino, F. Vacca · 2003
The growing interest in video standards has fostered many research activities towards efficient transform architectures. Many works have been proposed concerning the discrete cosine transform (DCT); however the need is felt for efficient cores, ready to be embedded into systems on chip (SoC). To grant maximal interoperability among different cores, the proposed DCT one has been designed to be wishbone compliant. A reconfigurable systolic 2D-DCT architecture is proposed and physical implementation results on XILINX Virtex-E FPGA are given. As far as performance is concerned, this core is able to process 128 XGA (1024/spl times/768) frames/s running at 110 MHz.