HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core
Lars Friebe, H.-J. Stolberg, Mladen Bereković, Sören Moch, Mark B. Kulaczewski, A. Dehnhardt, R. Pirsch · 2004
The HiBRID-SoC integrates three fully programmable processor cores, each optimized towards a particular class of algorithm: the HiPAR-DSP for DSP oriented functions, the macroblock processor for block oriented algorithms, and the stream processor for bitstream processing. Dedicated interface units for SDRAM, serial Flash, and host system access are connected via a 64 bit AMBA AHB system bus with the processor cores. Dual-port memories between the processor cores facilitate fast data and control information exchange between the cores. The HiBRID-SoC is fabricated in a 0.18 /spl mu/m 6LM standard-cell technology, occupies about 82 mm/sup 2/, and operates at 160 MHz.