Stride permutation networks for array processors
Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala · 2004
In several digital signal processing algorithms, the computation is done in consecutive stages where each stage consists of several parallel computational nodes. The computation stages are decoupled by permutation stages where stride permutations are commonly used because of their regularity. If such algorithms are computed with reduced number of processing elements, where one element computes several computational nodes, the permutation, instead of being hardwired, requires a storage of intermediate data elements. In this paper, register-based stride permutation networks are proposed for array processors, where the storage requirement in the permutation network is relatively small, and thus, the memory-based structures are expensive solutions. The proposed networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Furthermore, the networks are generated without heuristics which makes them attractive for automated design procedures. 1.