Partial reconfiguration on FPGAs in practice — Tools and applications
Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele · 2012
Abstract. Run-time reconfiguration of FPGAs has been around in aca-demia for more than two decades but it is still applied very seldom in industrial applications. This has two main reasons: a lack of killer applica-tions that substantially benefit from run-time reconfiguration and design tools that permit to quickly implement corresponding reconfigurable sys-tems. This tutorial gives a survey on state-of-the-art trends on reconfig-urable architectures and devices, application specific requirements, and design techniques and tools that are essential for implementing partial run-time reconfiguration on FPGAs. This is followed by a demonstra-tion of the floorplanning and constraint generation tool GoAhead. Fur-thermore, the tutorial will reveal several applications that benefit from partial reconfiguration, including network data processing, digital signal processing, cognitive radio, and systems on a reconfigurable chip. For these applications, the individual challenges and implementation issues are presented together with the achieved results. This tutorial demon-strates that partial FPGA reconfiguration is beneficial and applicable in industrial systems. 1