A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST
Hideki Sakakibara, Masato Nakayama, M. Kusunoki, K. Kurita, H. Otori, M. Hasegawa, S. Iwahashi, Keiichi Higeta, T. Hanashima, Hideki Hayashi, K. Kuchimachi, Keijiro Uehara, T. Nishiyama, M. Kume, K. Miyamoto, E. Kamada · 2003
A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.