A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains
Suk Jin Kim, Jeong Gun Lee, Kiseon Kim · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2004
Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 μm CMOS technology to verify performance analysis of the proposed synchronization.