Fast testable design for SRAM-based FPGAs
Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito · 2000
This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAMmemor is modified so that the FPGA may have the facility to loop the testingconfigur2U24 data inside the chip. The full testing of the FPGA is achieved by loading typically only onecar48O8) chosen testingconfigurUUOD data instead of the whole configurO)BDN data. Theother rher2D configur929OO