Architecture features and evaluation of a variable-topology multiprocessor for real-time applications
Hsiao-Chen Chung, James Rakes, P.J. Zievers, Yin-Kuan Lin, Chuan-lin Wu · 2002
This paper presents design and evaluation of a decentralized control mechanism of a phase reconfigurable multiprocessor architecture. The motivation stems from two facts. First, the delay caused by global synchronization and traffic congestions, using contemporary interconnection networks, is indeterministic. The indeterministic nature makes it very awkward to use the due systems for real-time applications. Second, many real-time applications require multi-phase computations which can only be implemented with a system that has a variable-topology capability. New technology is needed for an effective phase transition since existing phase transition methods involve too much overhead. A unique interconnection feature is used in the architecture. We design and implement an active crossbar communication processor which encodes a set of communication instructions. The new interconnection network approach provides an apt phase-reconfiguration method. The new method is distributed in nature and does not require a global control bus that is a time consuming feature as verified in many existing systems. Multiprocessor organization, computation model and languages features of this variable topology architecture are exploited. Conjugate-gradient algorithm for solving a linear system equations is used to provide evaluation and comparison.>