Hardware Implementation of Lifting-based DWT for JPEG2000
Yong-Jun Kim, Duck-Jin Chung · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
As an inevitable and time-consuming component in JPEG2000, lifting-based 2D discrete wavelet transform (DWT) is often implemented with a devoted hardware in systems which require real time processing. However, most of the proposed architectures for 2D DWT failed to achieve high performance because they didn't fully utilize the potential parallelism within the algorithm. The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. In this paper, we propose a parallel architecture which can make use of the parallelism in 2D DWT algorithm. The architecture consists of one address control sequencer, two row processors, two column processors, and two memory modules. These processors are organized as a fully interleaving pipeline being capable to produce fast results. The architecture has been coded in Verilog HDL, and then verified successfully by the platform of Xilinx of version 1.0i and ModelSim of version SE 6.0c. Finally, it was realized with the FPGA device of Spartan-3E XC3S500E form Xilinx Corp.