A reconfigurable public-key cryptography coprocessor
Xiaoyang Zeng, Chao Chen, Qianling Zhang · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
A new RSA/ECC coprocessor with the characteristic of reconfiguration is proposed in this paper, which can meet the requirements of both GF(p) and GF(2'") fields and perform the prevalent cryptographies such as RSA and ECC. The coprocessor has the merit of reconfigurable architecture, and it can perform the modular multiplication from 32-bit to 512-bit without any modification to its hardware. Based on 0.35 /spl mu/m CMOS technology, area of the coprocessor is about 45K gates, and system frequency can up to 100MHz, the 512-bit modular multiplication achieve 190kbps and the 233-bit ECC encryption rate of 50kbps.